Monostable transistor triggered circuits



July 7, 1953 A, w, L0

MONOSTABLE TRANSISTOR TRIGGERED CIRCUITS 3 Sheets-Sheet l Filed July l,1952 F/SE i211 ii Ill 2 0 0 u. hkw nx f ,hwk WQ 0 .wkvu \.v\ .vx a.. M ns I? l f 7.. f y ...Il v 0 M M 0 a a M a .P x .Qk xux .wkx y INVENTORATTORNEY July 7,1953 A. w. Lo 2,644,895

MoNosIABLE TRANSISTOR TRIGGERED CIRCUITS Filed .Jul'y 1, 1952sheets-sheet 2 INVENTOR ATTORNE Patented July 7, 1953 MONOSTABLETRANSISTOR TRIGG-'ERED CIRCUITS Arthur W. Lo, Haddoneld, N. J.,Yassigner to Radio Corporation of America, a corporation of DelawareApplication July 1, 1952, Serial No. 296,586

` (c1. lsoi- 88) 19 Claims.

i This invention relates generally to triggered circuits, andparticularly relates tov monostable vtransistor circuits of the -typeemploying single current-multiplication transistors.

Various transistor circuits are known which `employ a singlecurrent-multiplication transistor to provide either monostable orbistable triggered circuits. A bistable circuit of this type isdisclosed `and claimed in the patent to Eberhard 2,533,001. The patentto Rack 2,579,336 discloses and claims astabilized transistor triggeredcircuit which may -be either monostable or bistable.

The llatter patent indicates that available transistors exhibitconsiderable differences in their characteristics such, for example, -asthe emitter current vs. emitter voltage characteristic. Many of theprior art transistor triggered circuits require adjustment of thecircuit constants to compensate for the diierent characteristics of eachindividual transistor,

stantially Zero resistance in the external base circuit during its lowcurrent conduction state which, in turn, tends to cause the-emittercurrentemitter voltage curve to pass through the origin of thecoordinates. However, this circuit is comparatively complicated and maystill require adjustment of the circuit constants Ato compensate thevdifferences of the characteristics Vor individual transistors.

In a copending application oi A. W. Lo rand R. P. Moore, Jr., Serial No.296,585'1ed July 1, 1952, entitled Monostable Transistor Circuits andfiled concurrently herewith, there is disclosed and claimed a transistorcircuit which is effective to overcome the drawbacks Vof prior arttriggered circuits. In particular, vthe Lo-Moore transistor circuit doesnot require'adjustment lof the circuit constants to compensate fordifferences of the characteristics of individual transistors. I-Iowever,the transistor triggered circuit disclosed in the `copen'dingapplication above referred to vrequires a source of trigger pulseshaving a lcomparatively low resistance because the pulse source formspart of the emitter circuit.

It is a principal object or" the present invention to provide improvedmonostable triggered circuits employing 'a current-multiplicationtransistor.

A further object of the invention is to provide a monostable transistorcircuit wherein the source of the trigger pulses need not have a lowresistance and which will reshape and amplify the trigger pulses.

Another object of the invention is to kprovide a monostable triggeredcircuit of the `type referred The Rack lcircuit is intended to overcomethis defect by providing sub- ZZ to, which will develop an output pulseof Vpredetermined amplitude and width in response to a trigger `pulseandwhere the leading edge'of the output pulse may be delayed withrespect `to vthat of the trigger pulse.

A monostable trigger circuit in accordance with the present inventioncomprises a current-multiplication transistor. An external networkinterconnects Vthe transistor electrodes with a common junction pointsuch asiground and includes abase impedance element and a collectorimpedanceelement which seri/esas the output load. A suitable source ofvoltage such as a battery is .provided in series with the base andcollector impedance elements to bias the collector in the reversedirection with respect tothe base. The base impedance elementv may bearesistor and provides for regenerationas explained in the Eberhardpatent referred to.

`In accordance with the present invention, the emitter is connected tothe common junction point through suitable capacitive means, such as acapacitor. The source of trigger pulses is coupled across the base`impedance element. Accordingly, the emitter circuit is substantiallyopencircuited during the stable state of operation which corresponds tolow collector current. Since the emitter circuit is open-circuited,there isv substantially Zero emitter current low. By applying a triggerpulse across the base impedance element, the circuit is triggered Vintohigh conduction and the circuit is temporarily carried intoits-regenerative or unstable state. rThis unstable state will exist lfora lperiod or time vdetermined by the capacitance of the emittercapacitor, and during this time an output pulse is developed across thecollector or load impedance element.

Preferably, the source of trigger pulses is coupled to the base resistorthrough a crystal rectiier so that lthe-source is disconnected from the'transistor until a trigger pulse is applied. Furthermore, a crystalrectifier may be connected directly-between emitter and base and thisrectier is poled to be rendered conducting when a reverse voltage exists'betweenemitter and base. The provision of a crystal rectifierbetween'emitter and base will reduce the time required to condition thecircuit to be triggered by asucceeding pulse. It is also feasible toprovide an inductive output load thereby to Adelay the leading edge ofthe output pulse with respect to that ci the trigger pulse. Variousother modifications of the triggered circuit of the invention arefeasible which will be explained more in detail hereinafter.

The novel features that are considered characteristic of this inventionare set forth with particularity in the appended claims. The inventionitself, however, both as to its organization and method of operation aswell as additional objects and advantages thereof, will best beunderstood from the following description when read in connection withthe accompanying drawings, in which:

Figure 1 is a circuit diagram of a monostable triggered circuitembodying the present invenn tion;

Figure 2 is a graph illustrating the emitter voltage plotted as afunction of the emitter current;

Figure 3 is a graph illustrating output voltage pulses derived from thecircuit of Figure 1 under various conditions;

Figure 4 is a circuit diagram of a modified monostable circuit inaccordance with the invention which will develop an output pulse that isdelayed with respect to the trigger pulse;

Figure 5 is a graph illustrating voltages plotted with respect to timederived from the circuit of Figure 4 under different conditions;

Figure 6 is a circuit diagram of a monostable circuit in accordance withthe invention which will develop a single output pulse in response tothe closing of a switch;

Figures 7-9 are circuit diagrams of modified monostable transistorcircuits embodying the ino vention which permit control of the waveshape of the output pulse and of its direct current level;

Figure l is a graph illustrating output voltage as a function of timederived from the circuits of Figures '7 and 9 respectively; and

Figures 11 and 12 are circuit diagrams of monostable transistor circuitsin accordance with the invention wherein the emitter is `current biasedto increase the stability of the circuit and to discriminate againstundesired or spurious signals.

Referring now to the drawings in which like elements are designated bythe same reference characters throughout the figures and particular" lyto Figure l, there is illustrated a monostable triggered circuitincluding a transistor l0. Transistor I0 should be acurrent-multiplication vtransistor and may, for example, be a pointcontact transistor, that is, a transistor of the type where the emitterand collector electrodes are both in rectifying contact with thesemi-conducting body II. A current-multiplication transistor may bedened as a transistor where the short-circuit collector currentincrements are larger than corresponding emitter current increments. Thebody II may consist of a semi-conducting material such as germanium andpreferably is of the N type as will be assumed in the followingdiscussion. Emitter I2, collector I3 and base I4 are in contact withbody II. The details of manufacture and the mode 0I" operation of apoint contact transistor are well known and need not be furtherdescribed here.

Base resistor I is connected between ibase I4 and ground. Collectorresistor I6 is connected between collector I3 and a suitable source ofVoltage such as battery Il. Battery I'I is poled to apply a bias voltagein the reverse direction between collector I3 and base I4 and hence, itspositive terminal may be grounded while its negative terminal may beconnected through collector resistor I6 to collector I3. Battery II maybe bypassed for alternating-frequency currents by bypass capacitor I8. Apair of output terminals 2U is Iconnected across collector or loadresistor 16; one of the output terminals 20 may be ground* 4 ed, whilethe other one may be coupled to collector I3 through coupling capacitor2|.

The transistor circuit described so far is conventional. Usually a biasvoltage is applied between emitter I2 and base I4. However, inaccordance with the present invention, there need lbe no direct currentconnection between emitter I2 and ground. Instead, the emitter I2 isconnected to ground through capacitor 23. Accordingly, the transistorcircuit of Figure 1 is normally, that is, in its stable conditions,substantially open-circuited and no direct current bias voltage need beapplied between emitter I2 and base I4.

A pulse generator 25 which may, for example, develop negative triggerpulses 26 is coupled across base resistor I5. To this end, one terminalof pulse generator 25 may be grounded, while the other one is connectedto base I4 through coupling capacitor 21 and a rectiiier 28 such as acrystal rectifier connected in series. Crystal rectifier 28 is poled tobe rendered conducting upon the arrival of a trigger pulse 26. Hence, ifthe trigger pulse 26 is of negative polarity, rectier 28 should be poledto be conducting when the voltage of the junction point betweencapacitor 21 and rectifier 28 is negative with respect to the voltage ofbase I4. It is, however, to be understood that rectiier 28 may beomitted. Furthermore, another rectier 30 such as a crystal rectifier maybe connected directly between emitter I2 and base I4. Rectier 30 shouldibe poled to become conducting when a voltage in the reverse directionexists between emitter I2 and base I4. In other words, the rectier 30should be poled to become conducting when the voltage of emitter I2 isnegative with respect to that of base I4. It will be understood,however, that rectifier 30 may be omitted because it is not essential tothe operation of the circuit of the invention.

The operation of the monostable triggered circuit of Figure 1 may beexplained by reference to Figure 2 where the emitter current Ie isplotted against the emitter voltage Ve, both being indicated inFigure 1. Ve is taken between emitter and ground. The characteristiccurve 32 of Figure 2 essentially resembles the curves shown in the Rackpatent above referred to. The characteristic curve 32 has a negativeresistance portion A which is bounded on either end by a positiveresistance portion B and C, respectively. The points D and E are theboundaries between the positive portion C and the negative portion A andbetween the negative portion A and the positive portion B respectivelyof 4curve 32. The portion of the curve between points D and F (point Fcorresponding to IezO) has been exaggerated. The point D corresponds toan emitter current Ie of approximately 0.05 milliampere and to anemitter Voltage Ve of about -1 to -3 volts. However, it will be seenthat if the load line of the circuit intersects point F, a stableoperation point will be obtained; in accordance with the presentinvention this is accomplished.

Since the emitter circuit is substantially opencircuited for the stablestate of operation, the load line corresponds substantially to infiniteresistance and is represented by 18:0, that is. the vertical axisrepresents the load line which. of course, intersects the point F ofcurve 32. This stable state of operation corresponds to a state of lowcollector current with 18:0. At the same time, the emitter voltage Vehas a negative value.

Let it now be assumed that a negative trigger pulse 26 is applied to thecircuit of Figure 1. Ac-

cordingIy, the-voltage of base I4 is renderedmorenegative'andconsequently a currentIe -iiows between capacitor 23,emitter-I2 and base I4 in the direction Vindicated by the arrow inFigure l. As

long as this emitter current is greater than Ie (as shown in vFigure 2),the-circuit is triggered -into its unstable condition. The emittercurrent rwill now further increase. Since we vhave assumed thattransistor I is a current-multiplica- 'tion transistor, thecorresponding increase of the collector current will Abe larger thanthat of the emitter current. This large collector current flows throughbase resistor I'51and the :resulting voltage drop will drive the .basevoltage further Ain -the negative direction. Consequently, sincethe-voltage of .base1I4 is now negative with respect to that ofthejunction Apoint lbetween capacitor 21 and rectifier 128,-the rectier 28will .cease to conduct and pulsesource 25 is effectively 'discurrentwhich previously had a value greater than Ie' due to the trigger pulsesuddenly increases to Ie as shown .in Figure 2 due to this positivefeedback action. After the emitter current has thus suddenly increasedtoIe"l it decreases again exponentially because the emitter capacitor 23isl charged. Eventually the emitter current will vdecrease to avalueless than It (Figure 2) and then .the circuit rapidly returns again toits stable state of low `current conduction (point F on curve 32)lbecause the circuit is unstable'within the negative emitter resistanceportion A of the curve of Figure 2.

After'the circuit of Figure l has returned to its stable state ofoperation, there still remains a negative charge yacross capacitor .2.3.VIn other words, the voltage -of-emitter I2 is negative with respect tothat of base I4. This charge would normally leal; off slowly through theresistance which exists between emitter I2 and vbase I4. Thisresistance, however, is very high when Ythe emitter is biased in thereverse direction with respect to the base. Consequently, bythesprovision of rectiflerf itis possible to vrdischarge ca,- pacitor 23more rapidly. Asexplained hereinbe fore, rectier becomes conductingvwhen the emitter I2 is negative with respect to the base I4 and thiscondition prevails after the circuit has returned to its stablecondition. Consequently, the circuit is conditioned sooner to Yreceiveanother ytrigger pulse and the frequency of the trigger pulses may beincreased. However, as eX- plained hereinbefore, the rectier 30 is notessential to the operation of the circuit of the invention and may,therefore, be omitted.

From the above explanation, it will be evident that the pulse generator25 forms no part of the charge or discharge path of capacitor 23 and,therefore, the generator 25 may have any desired impedance. By providingarectiiier V23, the generator 25 is effectively disconnectedfromthetriggered circuit until another trigger pulse arrives. Trigger pulses25 may also be of 'positivepolarity in which case thenegative goingtrailingedge of each trigger pulse will trigger the circuit of Figure 1.

By way of example, the monostable circuit of Figu're'l may have a baseresistor I5 of 2,200 ohms and a collector resistor I6 of 5,600 ohms.However, it is also feasible to utilize a collectorresistorI6'of'verylowresistancesuch asf'lO ohms. In a Abattery Il and collectorI3.

circuit of this type :ahi'gh current output pulse has been obtainedwhichmay have a ,currentas high as one ampere. It has been found that such ahigh peak current does not `damage the transistor over long periods ofoperation. Ofcourse, theduration or width of the Voutputpulse is oftheorder of a few microseconds.

Referring now vto Figure 3 there Aareshown various curves illustratingthe collector voltage V@ plotted'as a functionr of time. The vfirstseries of curves 33, 34 and 35 was obtained'withithe circuit of Figure lwith an amplitude of the .trigger pulse of two volts and with a pulseduration vof 1/2, 2 and 5 microseconds respectively. The capacitance ofemitter capacitor 23 was 720fmicromicrofarads. The next set of curves36, 3'Irandz38 was obtained with the same circuit but with `an amplitudeof the trigger pulse of 20 volts; the

`pulse duration wasagain 1/2, 2 and '5 microseconds respectively. Thevalue of the emittercapacitor 23 was the same as above. Curves 40, 4|and-42 were also obtained with the circuit of Figure 1, but with acapacitance of emitter capacitor 23 of 470, 2,200 micro-microfarads and0.01 .microfarad respectively.

It will be seen from curves r33-38 that the amplitude and duration ofthe output pulses is substantially independent of the amplitudeandduration of the trigger pulses and depends on the capacitance ofemitter capacitor 23 as evidenced by curves 40-42.

For the conditions under which `curves 40-42 were obtained the outputpulse amplitude .is of the order of 40 volts, the output pulse riseAtime 0.02 microsecond and the output Apulse fall time 0.1 microsecond.The maximum voltage gain is 80 and the minimum trigger pulsevoltagerequired to triggerthe circuit is 0.5 volt. As shown by curves4042 the output pulse width is 0.25, 1.1 and 5 microseconds respectivelyfor acapacitance of emitter capacitor 23 or 470, 2,200 micro-microfaradsand 0.01 microfarad.

Referring now to, Figure 4 there is illustrated a modified monostabletransistor circuit ywhich makes it possible toA derive output pulseswhich are delayed with respect to the trigger pulses. Except for thecollector circuit the triggered circuit of Figure 4 is identical withthat of Figure 1.

In the collector circuit there is provided a resistor and an inductorllconnected in series between Inductor 46 forms the output load element.Capacitor 4'Ishown in dotted lines indicates the distributedfcapacitanceof inductor 46. Inductor 46 may be shunted by 'a resistor 48 to providedamping. Alternatively, a crystal rectifier 50 may be connected across.inductor 46 instead of resistor 48. `The output circuit preferablyincludesinductor 5I inductively coupled to inductor 46. Inductor 5I mayhave one terminal grounded while its other terminal is connected to oneof the output terminals 20 through capacitor 52 and rectifier 53connected in series. The circuit of Figure fl operates in the samemanner as does that of Figure 1. Referring .-now to Figure 5 there areillustrated curves 55 and 55. Curve 55 indicates the collector voltageVe as a. function of'time and curve 56 shows the `ouput voltage V0 (seeFigure 4) as a function of time. The leading edge of `curve 55 isdeveloped in response to a trigger pulse and the negative peak of curve55 corresponds to the instant when the circuit of Figure 4 returns toits stable state, that is, when the collector current is suddenlyreduced. The voltage developed .across output inductor 5I is shown bycurve 56. Inductors 46 and 5I preferably are wound in such a manner thatthe voltage V is reversed with respect to the collector voltage Vc asindicated in Figure 5. Rectifier 53 essentially operates as a clipper toremove or clip off the negative portion of output voltage curve 56.Consequently, a positive voltage peak is developed in response to thetrailing edge of the collector voltage curve 55.

Inductor 46 in combination with capacitor 41 forms a resonant circuitwhich tends to oscillate in response to the sudden changes of thecollector current. These oscillations can be damped in any conventionalmanner, for example, by damping resistor 48. Alternatively, rectiiier 50may be provided which will remove the positive portion of curve 55 byproviding a low impedance path for such a voltage. In case rectifier 50is utilized, the rectier 53 in the outp-ut circuit may be omittedbecause in that case, only the trailing edge of curve 55 will appear inthe output voltage.

Curves 55 and 55 were obtained with the circuit of Figure ll having anemitter capacitor 23 of 0.25 microfarad. In that case, the time delay ofthe output pulse with respect to the trigger pulse is almost 100microseconds. Curves 51 and 58 corresponding respectively to curves 55and 56 were obtained with an emitter capacitor of 0.01 microfarad.Consequently, the time delay is smaller and is of the order of l0microseconds. With the circuit of Figure 4 delay times of the outputpulse of between 1/2 and 100 microseconds may be obtained. With a valueof the emitter capacitor of 470 micro-microfarads, 0.01 microfarad and0.25 microfarad respectively, time delays of 0.5, 8.5 and 95microseconds were obtained with an output pulse amplitude of l0, 35 and40 volts and with a maximum voltage gain of 20, 70 and 80 respectively,the minimum amplitude of the trigger pulse necessary to initiate a cycleof 0.5 volt in all cases.

Referring now to Figure 6 there is illustrated a monostable triggercircuit which will develop aV single output pulse when a switch isclosed. The circuit of Figure 6 again has a base resistor I5 and acollector resistor I5 across which the output pulse is developed. Theemitter circuit is normally open. The emitter capacitor 23 has oneterminal connected to ground while its other terminal is connected tothe arm 60 of a switch movable between two iixed contacts 6I and 62.Contact 6I is grounded while contact 62 is `connected to emitter I2.

With the emitter circuit open, a small collector current ilows throughbase resistor I5 to maintain base I4 at a negative potential. When theswitch arm 60 is now moved from the position shown in Figure 6 tocontact 62, a positive current flows into the emitter because theemitter isnow rendered positive with respect to the base. The Abase ismaintained at a negative potential due to the voltage drop of thecollector current across base resistor I5. The circuit of Figure 6 againoperates in the manner previously described.

It is also feasible to connect switch contact 6I to the positiveterminal of a battery, thereby to provide a trigger pulse of largeramplitude. However, if the resistance of base resistor I5 issufficiently large, this will not normally be re quired. The rectifier33 has been omitted in the circuit of Figure 6.

Figure 7 illustrates a monostable circuit which is similar to that ofFigure 1. Rectier 30 has again Ibeen omitted and the battery I1 is nowconnected between base resistor I5 and ground rather than betweencollector resistor I6 and ground. In this case the negative terminal ofbattery I1 is grounded to apply a positive voltage to base I4. Aninductor 65 may be connected in series between collector resistor I6 andcollector I3.

Disregarding inductor 65, the circuit of Figure 7 operates in the samemanner as that of Figure 1. However, since battery I1 is now providedbetween base resistor I5 and ground, it is not necessary to provide acoupling capacitor 2| in the output circuit. In other words, the outputvoltage does not include the supply voltage. Thus, the circuit of Figure'7 may be desirable for driving direct current circuits or amplifiers.Curve 66 of Figure l0 illustrates the collector voltage pulse as afunction of time obtained from the circuit of Figure 7 in the absence ofinductor 65.

The circuit of Figure 8 is similar to that of Figure 7 except that abattery 66 is connected between base resistor I5 and ground whileanother battery 61 is connected between collector resistor I6 andground. Batteries 66 and 61 may be bypassed for alternating-frequencycurrents by bypass capacitors 68 and 10 respectively. The circuit ofFigure 8 makes it possible to adjust the direct current level of theoutput circuit to any desired value by proper selection of the magnitudeof batteries 66 and 61.

The inductor 65 shown in the circuit of Figure 7 has the purpose tomodify the wave shape of the output voltage as shown by curve 12 ofFigure l0 and illustrating the output voltage Vo as a function of time.It will be observed that the output voltage overshoots on the down swingand eventually becomes negative. The width of the output pulse 12 is nowdetermined both by the capacitance of emitter capacitor 23 and by theinductance of inductor 65.

The circuit of Figure 9 is similar to that of Figure 7 except that thecollector inductor 65 has been replaced by an LC network 13 in theemitter circuit. The LC network 13 includes capacitor 23 connectedbetween emitter I2 and ground and a series inductor 14 having its freeterminal bypassed to ground by another capacitor 15. This pi network 13may be considered a portion of a transmission line. The collectorvoltage wave shape obtained from the circuit of Figure 9 is shown at 16in Figure l0.

In some monostable circuits discrimination against undesired spurioussignals may be more important than the trigger sensitivity. To this end,the emitter may be current biased to insure that the transistor circuitremains in its stable or quiescent state until a trigger pulse exceedinga prescribed amplitude level is applied to the circuit. Such triggeredcircuits are shown in Figures 11 and l2 and reference is now made toFigure 1l. In accordance with Figure 11 a resistor 18 is connecteddirectly between collector I3 and emitter I2. Accordingly, the emitterI2 is maintained at a voltage which is negative with respect to that ofbase I4. The resistance of resistor 18 preferably is high. Consequently,a negative current flows into the emitter, that is, a current flows frombase I4 to emitter I2 as defined by the conventional direction ofcurrent flow.

It will be obvious that for the circuit of Figure 11 the load line is nolonger given by 12:0 because Ie nowhas'a negative value. Furthermore,there is-a deiinite resistance in theemitter circuit andthe load linewill intersect the curve portion C of the curve 32 of Figure 2 to theleft of point F, and the load line will have avslope corresponding toapositive resistance. Itwill also beobvious that the trigger pulse mustprovide a slightly larger current to trigger the circuit past the pointD of the curve of Figure 2. Resistor 18, however, has little effect onthe operation of the circuit after it has been triggered into itsstateof high conduction.

A modification of the circuit of' Figure 11 is illustrated in Figure 12.Battery l1 is provided between base resistor I5 and ground and areslstorv 80 is connected in shunt across emitter capacitor 23. Resistor80 will again maintain emitter l2 at a-potential that is negative withrespect toA that of base I4 which is maintained at a positive potential.Consequently, the circuit ofA Figure 12 is again biased by a negativeemitter currentv and its operation is the same'as that previouslydescribed in connection with Figure 11.

There have thus been disclosed monostable triggered circuits utilizing acurrent-multiplication transistor. The pulse generator which developsthe trigger'pulses may be of high impedance and the amplitude andduration of the outputv pulses is determined essentially by thecapacitance of an emitter capacitor and by the magnitude ofthe collectorbias voltage. The output. pulses maybedelayed with respect to thetrigger pulses and the wave shape may be controlledin many ways. It isalso feasible to control' the direct current level of the output voltageand todiscriminate against spurious pulses. The monostable circuits ofthe invention may be utilized for amplifying andshaping trigger pulseswhich may have any duration and which need not haveY a high amplitude.

What is claimed is:

1. A monostable triggered circuit comprising a currentemultiplicationtransistor including a semi-conducting body, a base electrode, anemitter electrode and a collector electrode in contact with said body,an external network interconnecting said electrodes with a commonjunction point and including a nrst impedance element. connected betweensaid base electrode an'dsaid junction point, a second output impedanceelementV connected between said collector electrode-and saidv junctionpoint, a source oi' voltage connected in series with said first andsecond impedance elements and poled to apply a voltage in the reversedirection between said collectorn and` base electrodes, capacitive meansconnected between said emitter electrode and said junction point,whereby the emitter circuit isv substantially open-circuited for directcurrents, said circuit having a stable state of low current` conductionand an instable state of high current conduction, the external emittercircuit beingA substantially open-circuited during said stable statecorresponding to substantially zero emitterv current, and means coupledacross said first impedance element for applying triggered pulses,whereby the application of a trigger pulse carries said triggeredcircuit temporarily into said instable state for a` period ofI timedetermined by the capacitance of said capacitor to develop an outputpulse across said second impedance element.

2. A triggeredv circuit as defined in claim 1 whereinlsaid firstimpedanceelement is la resistor.

3. A'. triggered circuit as defined' in claim 1 10 wherein said secondimpedance element is a resistor.

4. A triggered circuit as defined in claim'` 1 wherein said secondimpedance element includes aninductor.

5. A triggered circuit as defined in claim 1 wherein said source ofvoltage is connected between said second impedance element' and saidjunction point.

6'. A triggeredV circuit as deined in claim 1 wherein said source' ofvoltage is connected between said iirst impedance element and saidjunction point.

7. A triggered circuit as dened in claim 1 wherein said source ofvoltage has an. intermediate point connected to said junction point.

8. A monostable triggered circuit comprising a current-multiplicationtransistor including a semi-conducting body, a base electrode, anemitter electrode and a collector electrode in contact with said body,an external network interconnecting said electrodes with a commonjunction point and including a rst impedance element'connected betweenrsaid base electrodeand said junction point, a second output impedanceelement connected between said collector electrode and said junctionpoint, a source of voltage connected in series with said rst and secondimpedance elements and poled to apply a Voltage in the reverse directionbetween said collector and base electrodes, a rst capacitor connectedbetween said emitter electrode and said junction point, said circuithaving a stable state of low current conduction and an instable stateofv high current conduction, the external emitter circuit beingsubstantially opencircuited during said stable state corresponding tosubstantially zero emitter current, a first rectier connected directlybetween said emitter andbase electrodes and poled to be renderedconducting when a reverse bias voltage exists between said emitter andbase electrodes, a source of trigger pulses, a second rectier and asecond capacitor connected in series with said source of pulses acrosssaid first impedance element, and said second rectifier being poled tobe rendered conducting upon arrival of one of the trigger pulses,whereby the-application of a trigger pulse carries said triggeredcircuit temporarily into said instable state for a period of timedetermined by the capacitanceV of said capacitor to develop an outputpulse across said second impedance element.

9. A monostable triggered circuit comprising a current-multiplicationtransistor including a semi-conducting body, a base electrode, anemitter electrode and a collector electrode in contact with said body,an external network interconnecting said electrodes with a commonjunction point and including a first impedance element connected betweensaid base electrode and said junction point, a resistor and an outputinductor connected in series between said collector electrode and saidjunction point, a source of Voltage connected in series with said iirstand second impedance elements and poled to apply a voltage in thereverse direction between said collector and base electrodes, a rstcapacitor connected between said emitter electrode and said junctionpoint, said circuit having a stable state of low current conduction andan instable state of high current conduction, the external emittercircuit being substantially open-circuited during said stable statecorresponding to` substantially Zero emitter current, a first rectier`connected directly between said emitter and base electrodes and poled tobe rendered conducting when a reverse bias Voltage exists between saidemitter and base electrodes, a source of trigger pulses, a secondrectifier and a second capacitor connected in series with said source ofpulses across said rst impedance element, and said second rectifierbeing poled to be rendered conducting upon arrival of one of the triggerpulses, whereby the application of a trigger pulse carries saidtriggered circuit temporarily into said instable state for a period oftime determined by the capacitan-ce of said capacitor to develop anoutput pulse across said output inductor.

10. A triggered circuit as defined in claim 9 wherein means is providedfor damping the oscillations set up in said output inductor due toVariations of the collector current in response to the arrival of atrigger pulse.

1l. A monostable triggered circuit comprising a current-multiplicationtransistor including a semi-conducting body, a base electrode, anemitter electrode and a collector electrode in contact with said body, afirst impedance element connecting said base electrode to a commonjunction point, a second output impedance element connecting saidcollector electrode to said junction point, a source of voltageconnected serially with said iirst and second impedance elements forapplying a bias voltage in the reverse direction between said collectorand base electrodes, a capacitor having one terminal -connected to saidjunction point, and switch means for selectively connecting the otherterminal of said capacitor either to said junction point or to saidemitter electrode, whereby the emitter circuit is open when said otherterminal is connected to said junction point and whereby an output pulseof predetermined width and amplitude is developed across said secondimpedance element when said other terminal is connected to said emitterelectrode.

12. A monostable triggered circuit comprising a current-multiplicationtransistor including a semi-conducting body, a base electrode, anemitter electrode and a collector electrode in contact with said body, aresistor connecting said base electrode to a common junction point, anoutput impedance element connecting said collector electrode to saidjunction point, a source of voltage connected serially with saidimpedance element between said collector electrode and said junctionpoint for applying a bias voltage in the reverse direction between saidcollector and base electrodes, a capacitor having one terminal connectedto said junction point, and switch means for selectively connecting theother terminal of said capacitor either to said junction point or tosaid emitter electrode, whereby the emitter circuit is open when saidother terminal is connected to said junction point and whereby an outputpulse of predetermined width and amplitude is developed across saidimpedance element when said other terminal is connected to said emitterelectrode.

13. A monostable triggered circuit comprising a current-multiplicationtransistor including a semi-conducting body, a base electrode, an emit-'ter electrode and a collector electrode in contact with said body, anexternal network interconnecting said electrodes with a common junctionpoint and including a first resistor connected between said baseelectrode and said junction point, an inductor and a second outputresistor connected in series between said collector electrode and saidjunction point, a source of voltage connected in series with saidresistors and poled to apply a voltage in the reverse direction betweensaid collector and base electrodes, a capacitor connected between saidemitter electrode and said junction point, and a source of triggerpulses coupled across said rst resistor, said circuit having a stablestate of low current conduction and an instable state of high currentconduction, the external emitter circuit being substantiallyopencircuited during said stable state corresponding to substantiallyZero emitter current, whereby the application of a trigger pulse carriessaid triggered circuit temporarily into said instable state for a periodof time determined by the capacitance of said capacitor to develop anoutput pulse across said output resistor.

14. A monostable triggered circuit comprising a current-multiplicationtransistor including a semi-conducting body, a base electrode, yanemitter electrode and a collector electrode in contact with said body,an external network interconnecting said electrodes with a commonjunction point and including a resistor connected between said baseelectrode and said junction point, an output impedance element connectedbetween said collector electrode and said junction point, a source civoltage connected in series with said resistor and said impedanceelement and poled to apply a voltage in the reverse direction betweensaid collector and base electrodes, an LC network including a nrstcapacitor connected between said emitter electrode and said junctionpoint, said LC network including an inductor and a second capacitorconnected across said iirst capacitor, and a source ci ytrigger pulsescoupled across said resister, said circuit having a stable state of lowcurrent conduction and an instable state of high current conduction, theexternal emitter circuit being substantially open-circuited during saidstable state corresponding to substantially zero emitter current,whereby the application of a trigger pulse carries said triggeredcircuit temporarily into said instable state for a period of timedetermined by the capacitance of said capacitor to develop an outputpulse across said output impedance element.

15. A monostable triggered circuit comprising a current multiplicationtransistor including a semi-conducting body, a base electrode, anemitter electrode and a collector electrode in contact with said body,an external network interconnecting said electrodes with a commonjunction point and including a iirst resistor connected between saidbase electrode and said junction point, an output impedance elementconnected between said collector electrode and said junction point, asource of voltage connected in series with said resistor and saidimpedance element and poled to apply a voltage in the reverse directionbetween said collector and base electrodes, a capacitor connectedbetween said emitter electrode and said junction point, a source oftrigger pulses coupled across said iirst resistor, said circuit having astable state of low current conduction and 4an instable state of highcurrent conduction, and means including a seccnd resistor connected tosaid emitter electrode for applying to said emitter electrode duringsaid stable state of conduction a voltage to bias said emitter electrodein the reversedirection with respect to said base electrode.

16. A monostable triggered circuit comprising a current-multiplicationtransistor including a semi-conducting body, a base electrode, anemitter electrode and a collector electrode in contact with said body,an external network interconnecting said electrodes with a commonjunction point and including a first resistor connected between saidbase electrode and said junction point, output innedance elementconnected between said collector electrode and said junction point, asource of voltage connected in series with said impedance elementbetween said collector electrode and said junction point and pole-d toapply' a voltage in the reverse direction between said collector andbase electrodes, a capaci-tor connected between said emitter electrodeand said junction point, said circuit having a stable state of lowcurrent conduction and an instable state of high current conduction, asource of trigger pulses coupled across said nrst resistor, and a secondresistor connected directly between said collector and emitterelectrodes for biasing said emitter electrode in the reverse directionwith respect to said vbase electrode during said stable state ofconduction.

17. A monostable triggered circuit comprising a current-multiplicationtransistor including a semi-conducting body, a base electrode, anemitter electrode and a collector electrode in contact with said body,an external network interconnecting said electrodes with a commonjunction point and including a rst resistor connected between said baseelectrode and said junction point, an output impedance element connectedbetween vcollector electrode and said junction point, a source ofvoltage connected in series with said iirst resistor between said baseelectrode and said junction point and, noled to apply la voltage in therevrse direction between said collector and base electrodes, a capacitorconnected between emitter electrode and said junction point, saidcircuit lia-ving a stable state of low current eonductionand an instablestate of high current conduction, a source of trigger pulses coupledacross said first resistor, and a second resistor connected across saidcapacitor for biasing said emitter electrode in the reverse directionwith respect to said base electrode during said stable state ofconduction.

i8. A triggered circuit as defined in claim 16 wherein the resistance ofsaid second resistor is relatively high.

19. A triggered circuit as defined in claim 17 wherein the resistance ofsaid second resistor` is relatively high.

ARTHUR W. LG.

No references cited.

